The present invention relates to a dynamic standard cell. More particularly, the present invention relates to a dynamic logic circuit including a dynamic standard cell library.
In general, soft core (for example, behavioral or RTL code) may perform place and routing (P&R) using standard libraries in order to design chips. A set of conventional library cells may include basic cells such as AND, OR, NOR, INVERTER, and the like, complex cells such as OAI (OR/AND/INVERTER), AOI (AND/OR/INVERTER), and the like, and storage elements such as master-slave flip-flop, latch, and the like.